I translate architectural concepts into cycle-accurate RTL and drive them through synthesis, placement, and routing. From behavioural description to tape-out ready silicon.
ECE undergraduate at Saveetha Engineering College (2023–2027) specializing in RTL Design, FPGA implementation, and ASIC physical design. My primary focus is on verifiable correctness, clean synthesizable code, and complete end-to-end silicon execution under strict PPA constraints.
End-to-end implementation of a 32-bit RISC-V (RV32I) 5-stage pipelined processor. Integrated with AMBA/APB interconnect, UART, SPI, and GPIO peripherals. Successfully driven through the complete Cadence ASIC Physical Design flow.
Finalist project for SAKEC x ChipMonk hackathon. A highly optimized 5-stage pipelined edge inference engine deployed on Spartan-7. Designed for minimal area footprint while maintaining deterministic real-time processing speeds.
Hardware/Software co-design for AI acceleration. The ARM Cortex-A9 delegates heavy matrix computations to custom FPGA fabric via AXI-HP DMA, achieving massive performance improvements.
- Designed and verified an FPGA traffic-light controller from RTL to STA in Vivado, achieving Fmax >150 MHz.
- Implemented systematic RTL schematic checks and automated TCL timing constraints for rapid synthesis.
- Performed rigorous CDC (Clock Domain Crossing) analysis across multiple clock domains, eliminating metastability in I/O logic.
- Executed mixed-signal circuit design and simulation in Proteus, resolving component faults via structured hardware diagnostics.
- Applied low-power design techniques and schematic optimization for efficient embedded deployments.
- Delivered complete PCB layout, schematic capture, and verified hardware prototypes.
